In a conventional computer system, data is written into (and read from) a number of memory arrangements via known interfaces. With the current advances in the microprocessor controlling/accessing technology, it is now possible to utilize data busses which provide a large amount of data to the components of the existing computer systems. Thus, current memory arrangements (which are either arranged in or communicating with the computer systems) are now capable of receiving, storing thereon and providing a large amount of data.
With the recent introduction of new processing arrangements (e.g., a non-uniform memory access system or a “NUMA” system), there have been a number of advances to improve the access speed to the conventional memory arrangements. Indeed, because of the operational speed of the processors, it would be disadvantageous to utilize any arrangement (that interacts with the memory arrangements) which would slow down the overall performance of the computing system. Memory access systems are now available which provide the communication to and from the processors at accelerated speeds so as to enable a high throughput of the data. One of the advantages of such high throughput of the data provided with the known memory arrangements is that the time delay for transmitting the data to and from the memory arrangements is substantially diminished.
Two such memory arrangements may be provided for interacting with the processors via respective bus lines. For example, if the processors provide the data to a memory controller, such controller may forward this data to the respective bus line to be accessed by the memory arrangements. Because the access time to these memory arrangements has now been accelerated, the data may be accessed by or provided to both of the memory arrangements simultaneously. If the access to the data is provided at an accelerated rate, and the current draw is too high in the output drivers of the corresponding memory controller of the memory arrangement, an undesirable noise may be introduced into the operation of the computer system. Such noise may cause a signal (which is provided to and received from the memory arrangements) to be captured in a corrupted state. Such occurrence is referred to as a simultaneous switching noise (“SSO”).
The SSO may effect the system performance because the excessive noise associated with the SSO can cause a bit error on an interconnect arrangement. In addition, such excessive noise may cause a voltage Vdd (which is provided for powering the bus) to sag, thus resulting in a temporary or even permanent performance degradation on the control circuits of the computer system. Such performance loss can effectuate a timing failure of portions of the computer system, or even the entire computer system.
Thus, the control of the memory arrangements is one of the important features in the computer systems which employ, e.g., the NUMA architectures. According to the present invention (and as described in further detail below), the above-described problems associated with the SSO can be substantially reduced or even eliminated by utilizing an effective memory management scheme. According to an exemplary embodiment of the present invention, it is possible to control the access to the data outputs of the memory arrangements for limiting the simultaneously switching output of these memory arrangements.